The present invention relates to asynchronous digital circuit design and in particular to asynchronous circuitry for interconnecting a variety of system resources in the context of a system-on-a-chip.
A so called “system-on-a-chip” (SOC) is typically designed with a number of modules, each of which has its own clock. For example, such a system might include a memory controller, an I/O interface (e.g., PCI or HyperTransport), internal peripherals (e.g., SRAM or computing logic), computing resources (e.g., one or more CPUs), and some kind of interconnect for allowing the modules to interact with each other. In a typical SOC, the memory controller might operate at 300 MHz, the I/O interface at 400 MHz, the internal peripherals at 600 MHz, and each of the CPUs at 1.1 GHz. This makes it very difficult to implement an efficient interconnect solution.
Conventional approaches to this problem involve the use of a high speed synchronous bus in which transmissions to and from the various system modules on the bus are synchronized. That is, such a bus typically employs a clock signal the value of which is constrained by specific ratios with the clock signals being synchronized. Not only is this synchronization difficult to achieve, as soon as the performance of any of the modules (which are typically associated with different vendors) changes, i.e., clock speed increases, the ratios of the synchronization solution no longer apply, and a completely new solution must be implemented.
In view of the foregoing, it is desirable to provide an interconnect solution for implementing SOCs which allows various system modules having independent clock domains to communicate effectively and efficiently. It is also desirable that any such interconnect solution be flexible with regard to changes in individual system module performance.